State machine abstraction from circuit layouts using BDD's: applications in verification and synthesis.
Timothy KamP. A. SubrahmanyamPublished in: EURO-DAC (1992)
Keyphrases
- state machine
- analog circuits
- state machines
- finite state machines
- model checking
- logic synthesis
- hardware designs
- fault tolerant
- digital circuits
- bounded model checking
- high level
- high speed
- formal verification
- binary decision diagrams
- face verification
- program synthesis
- texture synthesis
- pattern matching
- circuit design
- signature verification
- asynchronous circuits
- logic circuits
- verification method
- electronic circuits
- artificial neural networks