A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton.
T. K. PriyaP. Rajesh KumarK. SridharanPublished in: Microprocess. Microsystems (2006)
Keyphrases
- shortest path
- low cost
- shortest path problem
- hardware implementation
- road network
- shortest path algorithm
- weighted graph
- routing algorithm
- hardware architecture
- finding the shortest path
- betweenness centrality
- spatial networks
- minimal surface
- parallel computation
- geodesic distance
- parallel architecture
- hardware design
- field programmable gate array
- steiner tree
- source node
- travel time