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Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS.
Theodoros Chalvatzis
Kenneth H. K. Yau
Ricardo Andres Aroca
Peter Schvan
Ming-Ta Yang
Sorin P. Voinigescu
Published in:
IEEE J. Solid State Circuits (2007)
Keyphrases
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low voltage
cmos technology
random access memory
low power
high speed
power line
design considerations
power consumption
power management
power dissipation
mixed signal
image processing
atomic force microscopy
parallel processing
computer vision
image sensor
parallel computing