A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization.
Yang SongZhenyu LiuTakeshi IkenagaSatoshi GotoPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2006)
Keyphrases
- vlsi architecture
- low cost
- variable block size motion estimation
- low power
- block size
- low complexity
- variable block size
- motion estimation
- motion vectors
- mode decision
- real time
- search range
- vlsi implementation
- intra prediction
- motion compensation
- quadtree
- parallel architecture
- video sequences
- video coding
- inter frame
- bit rate
- macroblock
- motion field
- computational complexity
- high speed
- optical flow
- video coding standard
- coding efficiency
- block matching
- image sequences
- compressed domain
- power consumption
- rate distortion
- image quality
- image blocks
- error concealment
- reference frame
- video compression
- motion compensated
- image coding
- video data