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A 40 Gbps PAM-4 Receiver with 12-Tap Direct Decision Feedback Equalizer Employing 1.5-stage Slicers in 65-nm CMOS.
Zeliang Zhao
Xin Wu
Dengjie Wang
Ziqiang Wang
Chun Zhang
Xiangyu Li
Zhihua Wang
Published in:
ICTA (2021)
Keyphrases
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decision feedback
error propagation
soft decision
multipath
intersymbol interference
cmos technology
power consumption
low cost
high speed
bit error rate
silicon on insulator
multiresolution
image coding
error resilience
orthogonal frequency division multiplexing