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An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU.
Yasushi Ooi
Osamu Ohnishi
Yutaka Yokoyama
Yoichi Katayama
Masayuki Mizuno
Masakazu Yamashina
Hideo Takano
Naoya Hayashi
Ichiro Tamitani
Published in:
ICASSP (1997)
Keyphrases
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single chip
software implementation
cmos image sensor
low power
low cost
multimedia
control system
signal processor
computer vision
video sequences
vision system
mpeg standard
multiresolution
rate distortion
dynamic range
video codec