An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU.

Yasushi Ooi Osamu Ohnishi Yutaka Yokoyama Yoichi Katayama Masayuki Mizuno Masakazu Yamashina Hideo Takano Naoya Hayashi Ichiro Tamitani

Published in: ICASSP (1997)

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