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Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion.
Andrew B. Kahng
Puneet Sharma
Rasit Onur Topaloglu
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2008)
Keyphrases
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optimal placement
low cost
discrete optimization
high bandwidth
high speed
optimization algorithm
optimization process
programmable logic
analog vlsi
functional verification
search algorithm
evolutionary algorithm
global optimization
constrained optimization
vlsi implementation