Login / Signup
RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining.
Hiromu Miyazaki
Takuto Kanamori
Md. Ashraful Islam
Kenji Kise
Published in:
IEICE Trans. Inf. Syst. (2020)
Keyphrases
</>
instruction set
parallel processing
high speed
computation intensive
application specific
floating point
single chip
general purpose
website
color images
input output
parallel architecture
training stage
multi core processors