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An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI.
Zhao Chuan Lee
M. Sultan M. Siddiqui
Zhi-Hui Kong
Tony Tae-Hyoung Kim
Published in:
IEEE J. Solid State Circuits (2019)
Keyphrases
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cmos technology
high speed
decision support
low cost
dynamic environments
dynamic random access memory
information systems
data management
power consumption
low power
management system
data acquisition
information management
random access memory
nm technology