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Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET Technology.
Mitesh Limachia
Pathik Viramgama
Rajesh Amratlal Thakker
Nikhil Kothari
Published in:
VLSI Design (2017)
Keyphrases
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cmos technology
low voltage
low power
leakage current
random access memory
power consumption
embedded dram
power line
parallel processing
high speed
read write
silicon on insulator
image sensor
low cost
nm technology
power dissipation
design considerations
power management
cost effective
real time