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A Max Pooling Hardware Architecture Supporting Inference And Training For CNN Accelerators.
Sanghyun Kim
Eunchong Lee
Minkyu Lee
Kyungho Kim
Sang-Seol Lee
Sung-Joon Jang
Published in:
ISOCC (2023)
Keyphrases
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hardware architecture
field programmable gate array
hardware implementation
structured prediction
hardware architectures
bayesian networks
artificial intelligence
cellular neural networks
processing elements
pattern recognition
associative memory
computing systems