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An Approach for the Delay Simulation of D-Inverter in C-Ternary Logic Circuits.
Thanasin Bunnam
Arthit Thongtak
Published in:
CDES (2008)
Keyphrases
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logic circuits
low power
power dissipation
control algorithm
simulation model
gate array
image processing
pattern recognition
multistage
input output
power consumption
parallel computers
tunnel diode