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Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM.
Takao Nomura
Ryo Mori
Koji Takayanagi
Kazuki Fukuoka
Koji Nii
Published in:
IEEE J. Emerg. Sel. Topics Circuits Syst. (2016)
Keyphrases
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design principles
design process
wide range
main memory
design decisions
neural network
high speed
knowledge based systems
input output
engineering design
computer aided
key issues
design methodology