Login / Signup
Reliability studies of a 10nm high-performance and low-power CMOS technology featuring 3rd generation FinFET and 5th generation HK/MG.
Anisur Rahman
Javier Dacuña
Pinakpani Nayak
Gerald S. Leatherman
Stephen Ramey
Published in:
IRPS (2018)
Keyphrases
</>
low power
cmos technology
power consumption
high speed
low cost
low power consumption
single chip
signal processor
image sensor
power dissipation
digital signal processing
low voltage
mixed signal
parallel processing
power reduction
silicon on insulator
logic circuits
embedded dram