Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation.
Mehedi HasanMd. Jobayer HosseinMainul HossainHasan U. ZamanSharnali IslamPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2020)
Keyphrases
- low power
- logic circuits
- power dissipation
- single chip
- low cost
- power consumption
- low power consumption
- cmos technology
- high speed
- gate array
- digital signal processing
- vlsi architecture
- mixed signal
- nm technology
- real time
- analog to digital converter
- power reduction
- digital circuits
- embedded systems
- high power
- wireless transmission