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LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage.
Hye Rim Ji
Jong Seong Kim
Jung Yun Choi
Jee Hyong Lee
Published in:
ASPDAC (2024)
Keyphrases
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neural network
layout design
memory requirements
prediction accuracy
case study
memory usage
random walk
pattern recognition
connected components
neural network model
design process
prediction model
associative memory
graph structure
graph theoretic
memory size
analog to digital converter