Design of Single Node Upset Resilient Latch for Low Power, Low Cost and Highly Robust Applications.
Anwesh Kumar SamalSandeep KumarAtin MukherjeePublished in: ITC-Asia (2023)
Keyphrases
- low power
- low cost
- single chip
- low power consumption
- highly robust
- power consumption
- vlsi architecture
- logic circuits
- high speed
- digital signal processing
- cmos technology
- power reduction
- gate array
- high power
- mixed signal
- power dissipation
- wireless transmission
- hardware and software
- embedded systems
- signal processor
- vlsi circuits
- ultra low power
- digital camera
- real time
- design process
- digital circuits
- image sensor
- design methodology
- computer vision