Login / Signup
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond.
Yoshihide Komatsu
Yukio Arima
Tetsuya Fujimoto
Takahiro Yamashita
Koichiro Ishibashi
Published in:
CICC (2004)
Keyphrases
</>
low power
nm technology
power consumption
low cost
high speed
error analysis
error accumulation
hardware and software
power dissipation
power reduction
fuzzy logic
error rate
estimation error
digital signal processing
hardware software co design