A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits.
Rong LinPublished in: VLSI Design (2001)
Keyphrases
- low power
- non binary
- logic circuits
- delay insensitive
- high speed
- power consumption
- low cost
- constraint satisfaction problems
- vlsi circuits
- single chip
- cmos technology
- mixed signal
- power reduction
- parallel processing
- digital signal processing
- power dissipation
- binary representation
- frequent pattern mining
- gate array
- vlsi architecture
- arc consistency
- shared memory
- constraint satisfaction
- asynchronous circuits
- hidden variables
- decoding algorithm
- constraint propagation
- low power consumption
- image sensor
- distributed memory