Scaling Trends of the AES S-box Low Power Consumption in 130 and 65 nm CMOS Technology Nodes.
Dina KamelFrançois-Xavier StandaertDenis FlandrePublished in: ISCAS (2009)
Keyphrases
- cmos technology
- s box
- low power
- low power consumption
- power consumption
- low cost
- high speed
- advanced encryption standard
- low voltage
- block cipher
- initial conditions
- single chip
- efficient implementation
- power dissipation
- digital signal processing
- image sensor
- encryption algorithms
- ciphertext
- silicon on insulator
- real time
- encryption algorithm
- chaotic systems
- wireless sensor networks