A divide-and-conquer strategie for FPGA implementations of large MLP-based classifiers.
Javier EchanobeRaul FinkerInés del CampoPublished in: IJCNN (2015)
Keyphrases
- multi layer perceptron
- neural classifier
- highest accuracy
- hardware architectures
- neural network
- software implementation
- multilayer perceptron
- hardware implementation
- support vector
- training data
- efficient implementation
- low cost
- high speed
- machine learning algorithms
- feature set
- real time
- artificial neural networks
- decision trees
- feature selection
- training samples
- naive bayes
- multiple classifiers
- training examples
- test set
- hardware architecture
- classification algorithm
- radial basis function
- svm classifier
- field programmable gate array
- verilog hdl
- neural network model
- classification accuracy
- training set
- data sets
- classification rate
- supervised classification
- image processing algorithms
- classification method
- class labels
- radial basis function network
- shortest path
- knn
- fpga implementation
- feature extraction
- learning algorithm
- layer perceptron