Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering.
Sharareh ZamanzadehAli JahanianPublished in: VLSI-SoC (2013)
Keyphrases
- reverse engineering
- design methodology
- reverse engineer
- software engineering
- conceptual schema
- design process
- software maintenance
- computer aided design
- dynamic analysis
- object oriented
- single chip
- gene regulatory networks
- software product
- physical design
- circuit design
- information systems
- formal specification
- case study
- software engineers
- hardware architecture
- application specific