An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture.

Daisaku Seto Minoru Watanabe

Published in: ASP-DAC (2009)

Keyphrases

gate array
hardware implementation
low cost
memory requirements
management system
low power
dynamic environments
neural network
memory space
memory management
dynamic reconfiguration
associative memory
memory usage
random access
field programmable gate array
cmos technology
memory hierarchy