Reconfigurable system for high-speed and diversified AES using FPGA.
Ming-Haw JingZih-Heng ChenJian-Hong ChenYan-Haw ChenPublished in: Microprocess. Microsystems (2007)
Keyphrases
- high speed
- field programmable gate array
- hardware implementation
- low power
- low cost
- systolic array
- power reduction
- reconfigurable architecture
- digital signal
- frame rate
- real time
- general purpose
- reconfigurable hardware
- fine grain
- multi objective evolutionary
- high speed networks
- parallel computing
- data acquisition
- advanced encryption standard
- dynamic reconfiguration
- xilinx virtex
- encryption algorithm
- high speed camera