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Reconfigurable 1-Bit Processor Array with Reduced Wirng Area.
Nobuo Nakai
Masaki Nakanishi
Shigeru Yamashita
Katsumasa Watanabe
Published in:
ERSA (2005)
Keyphrases
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processor array
parallel implementation
parallel algorithm
mesh connected
multiscale
general purpose
low cost
array processor
artificial intelligence
color images
hardware implementation
parallel computers