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A Novel 400-Gb/s (100-Gb/s×4) Physical-Layer Architecture Using Low-Power Technology.
Masashi Kono
Akihiro Kambe
Hidehiro Toyoda
Shinji Nishimura
Published in:
IEICE Trans. Commun. (2012)
Keyphrases
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low power
high speed
cmos technology
nm technology
vlsi architecture
physical layer
power consumption
low cost
mixed signal
communication protocol
real time
low density parity check
channel coding
application layer
power dissipation
mac protocol
network architecture
error correction
key technologies
video sequences