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Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip.

Heiko ZimmerStefan ZinkThomas HollsteinManfred Glesner
Published in: IPDPS (2005)
Keyphrases
  • network on chip
  • multi processor
  • routing algorithm
  • network simulator
  • end to end
  • packet switched
  • high speed
  • real time
  • data transfer
  • sensor networks
  • processing units