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A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS.

Hao LiShuai ChenLiqiong YangRui BaiWeiwu HuFreeman Y. ZhongSamuel PalermoPatrick Yin Chiang
Published in: VLSIC (2014)
Keyphrases
  • duty cycle
  • high speed
  • nm technology
  • real time
  • cmos technology
  • low power
  • random access memory
  • bit budget