A high-speed pattern decoder in MPEG-4 padding block hardware accelerator.
Hyeon-Cheol MoJong-Sun KimLee-Sup KimPublished in: ISCAS (2) (2001)
Keyphrases
- high speed
- field programmable gate array
- high bit rate
- fpga implementation
- real time
- content addressable memory
- low cost
- mpeg avc
- multimedia
- video decoder
- hardware implementation
- low power
- video coder
- block size
- video coding standard
- embedded systems
- decoding process
- low complexity
- rate distortion
- video codec
- block matching
- compressed video
- video sequences
- video transcoding
- video coding
- pixel domain
- digital video
- error detection
- bitstream
- error concealment
- parallel implementation
- computing systems
- motion vectors
- motion compensated