A hardware-efficient ergodic sequential logic neuron network for brain prosthetic FPGA.
Yuta ShiomiHiroyuki TorikaiPublished in: ISOCC (2022)
Keyphrases
- low cost
- hardware implementation
- real time
- hardware design
- field programmable gate array
- markov chain
- software implementation
- human brain
- hardware and software
- computer systems
- hardware architectures
- massively parallel
- single chip
- programmable logic
- fpga implementation
- stationary distribution
- dedicated hardware
- parallel hardware
- abstraction layer
- input patterns
- digital circuits
- parallel architectures
- network structure
- logic programming
- neural network