A hardware-efficient architecture for embedded real-time cascaded support vector machines classification.
Christos KyrkouTheocharis TheocharidesChristos-Savvas BouganisPublished in: ACM Great Lakes Symposium on VLSI (2013)
Keyphrases
- real time
- support vector
- classification accuracy
- vlsi architecture
- learning machines
- large margin classifiers
- support vector machine
- low cost
- dedicated hardware
- cross validation
- generalization ability
- vlsi implementation
- hardware architecture
- svm classifier
- machine learning
- real time embedded
- feature selection
- feature vectors
- pattern recognition
- smart camera
- graphics hardware
- hardware implementation
- feature extraction
- multi class classification
- video rate
- support vector machine svm
- embedded processors
- fpga device
- control software
- standard pc
- fpga implementation
- feature space
- parallel architectures
- low latency
- svm classification
- processing units
- binary classification
- embedded systems
- supervised learning
- logistic regression
- real time systems
- training set
- hardware software
- training data
- digital signal processor
- text classification
- model selection
- learning algorithm