Login / Signup

Evaluating the efficiency of using TMR in the high-level synthesis design flow of SRAM-based FPGA.

André Flores dos SantosLucas Antunes TambaraFernanda Lima Kastensmidt
Published in: LASCAS (2017)
Keyphrases
  • high level synthesis
  • parallel architecture
  • design process
  • low cost
  • design space exploration
  • power consumption
  • design space
  • low power consumption
  • verilog hdl
  • computing environments
  • agent model