Image processing on a reconfigurable array of processors with wider bus networks.
Shung-Shing LeeShi-Jinn HorngHorng-Ren TsaiYu-Hua LeePublished in: Pattern Recognit. (1997)
Keyphrases
- image processing
- systolic array
- parallel algorithm
- image enhancement
- image processing operations
- low cost
- social networks
- digital image processing
- parallel processing
- signal processing
- reconfigurable architecture
- parallel architecture
- computer graphics
- pattern recognition
- general purpose
- computer vision
- image compression
- communication delays
- interconnection networks
- feature extraction
- heterogeneous networks
- image analysis
- machine vision
- real time
- image segmentation
- network design
- high resolution
- color images
- remote sensing
- scheduling problem
- image restoration
- operating system
- image registration
- denoising