An FPGA implementation of a custom JPEG image decoder SoC module.
G. KyrtsakasRoberto MuscederePublished in: CCECE (2017)
Keyphrases
- fpga implementation
- jpeg images
- hardware implementation
- compression algorithm
- discrete cosine transform
- field programmable gate array
- compressed images
- data hiding
- dct coefficients
- spatial domain
- image processing algorithms
- embedded systems
- lossy compression
- wireless channels
- pattern recognition
- low bit rate
- computational complexity