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The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage.
Rahul Rithe
Sharon Chou
Jie Gu
Alice Wang
Satyendra Datla
Gordon Gammie
Dennis Buss
Anantha P. Chandrakasan
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2012)
Keyphrases
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low voltage
random access memory
asynchronous circuits
design considerations
power line
leakage current
signal processing
power management
cmos technology
power consumption