Login / Signup

The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage.

Rahul RitheSharon ChouJie GuAlice WangSatyendra DatlaGordon GammieDennis BussAnantha P. Chandrakasan
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2012)
Keyphrases
  • low voltage
  • random access memory
  • asynchronous circuits
  • design considerations
  • power line
  • leakage current
  • signal processing
  • power management
  • cmos technology
  • power consumption