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A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications.
I-Chyn Wey
Lung-Hao Chang
You-Gang Chen
Shih-Hung Chang
An-Yeu Wu
Published in:
ISCAS (2) (2005)
Keyphrases
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high speed
shift register
low power
single chip
design process
cmos technology
real time
hardware and software
functional verification
programmable logic
high speed networks
physical design
circuit design
embedded systems
lightweight
computer systems
low cost
case study