Power minimization for dynamically reconfigurable FPGA partitioning.
Tzu-Chiang TaiYen-Tai LaiPublished in: ACM Trans. Embed. Comput. Syst. (2013)
Keyphrases
- power consumption
- power reduction
- high speed
- low cost
- hardware implementation
- systolic array
- real time image processing
- hardware architecture
- field programmable gate array
- objective function
- real time
- computational power
- artificial neural networks
- hardware design
- parallel architecture
- image segmentation
- case study
- digital signal
- computer vision