A Hardware-Efficient Programmable FIR Processor Using Input-Data and Tap Folding.

Oscal T.-C. Chen Li-Hsun Chen

Published in: EURASIP J. Adv. Signal Process. (2007)

Keyphrases

input data
single chip
low cost
parallel architectures
data sets
real time
general purpose
image processing
multi core processors
high speed
hardware and software
computer architecture
instruction set
hardware architecture
protein folding
filter bank
computationally efficient
image data
feature extraction