29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS.
Jun CaoDelong CuiAli NazemiTim HeGuansheng LiBurak ÇatliMehdi KhanpourKangmin HuTamer A. AliHeng ZhangHairong YuBen RhewShiwei ShengYonghyun ShimBo ZhangAfshin MomtazPublished in: ISSCC (2017)