An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training.
Haikuo ShaoJinming LuJun LinZhongfeng WangPublished in: ISVLSI (2021)
Keyphrases
- field programmable gate array
- training process
- hardware implementation
- parallel computing
- low cost
- hardware design
- training phase
- image processing algorithms
- general purpose
- test set
- embedded systems
- neural network
- smart camera
- high levels
- application specific
- online learning
- training set
- image processing
- surveillance system
- training algorithm
- supervised learning
- support vector
- training data
- machine learning
- data sets
- compute intensive