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A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic.

Harsh N. PatelAbhishek RoyFarah B. YahyaNingxi LiuBenton H. CalhounKazuyuki KumenoMakoto YasudaAkihiko HaradaTaiji Ema
Published in: ESSCIRC (2016)
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