A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction.
Benjamin P. HershbergKuba RaczkowskiKristof VaesenJan CraninckxPublished in: ESSCIRC (2014)
Keyphrases
- metal oxide semiconductor
- high speed
- circuit design
- power consumption
- cmos technology
- clock gating
- cmos image sensor
- low power
- integrated circuit
- silicon on insulator
- mixed signal
- low cost
- frequency band
- real time
- reduction method
- parallel processing
- high frequency
- neural network
- nm technology
- analog to digital converter
- power supply
- delay insensitive