A Low-delay Configurable Register for FPGA.

Zhi-Yin Lu Jia-Feng Liu Yunbing Pang Zheug-Jie Li Yufan Zhang Jin-Mei Lai Jian Wang

Published in: ASICON (2019)

Keyphrases

low delay
video coding
coding scheme
wyner ziv video coding
hardware implementation
rate control
distributed video coding
high speed
signal processing
rate distortion
low complexity
motion compensation
computer vision
inter frame
video streaming
coding efficiency