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An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs.

Kenji ShimazakiMitsuya FukazawaMakoto NagataShingo MiyaharaMasaaki HirataKazuhiro SatohHiroyuki Tsujikawa
Published in: CICC (2005)
Keyphrases
  • low power
  • low cost
  • high speed
  • asynchronous circuits
  • real time
  • data sets
  • power consumption
  • noisy data
  • image noise
  • nano scale
  • dynamic environments
  • infrared
  • noise reduction
  • noise level
  • additive noise