Transistor sizing strategy for simultaneous energy-delay optimization in CMOS buffers.
Longyang LinKien Trinh QuangMassimo AliotoPublished in: ISCAS (2017)
Keyphrases
- high speed
- power dissipation
- low power
- optimization strategies
- power consumption
- optimization strategy
- optimization algorithm
- simultaneous optimization
- optimization problems
- energy efficiency
- cmos technology
- power losses
- global optimization
- buffer size
- energy consumption
- constrained optimization
- circuit design
- energy saving
- optimization methods
- energy minimization
- low cost
- evolutionary strategy
- neural network
- power supply
- search strategy
- combinatorial optimization
- low voltage
- optimization method