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A 5.8nW, 45ppm/°C on-chip CMOS wake-up timer using a constant charge subtraction scheme.
Seokhyeon Jeong
Inhee Lee
David T. Blaauw
Dennis Sylvester
Published in:
CICC (2014)
Keyphrases
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high speed
analog vlsi
low cost
circuit design
charge coupled devices
single chip
low power
cmos technology
cmos image sensor
chip design
image sensor
high density
focal plane
mixed signal
neural network
power supply
low power consumption
random access memory
power consumption