A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology.

Bingrong Lyu Fan Ye Junyan Ren

Published in: ASICON (2023)

Keyphrases

cmos technology
low power
image processing
power consumption
low voltage
digital images
low cost
high speed
pattern recognition
design process
design methodology
spl times