FPGA implementation of layered low density parity check error correction codes.
Abdulsamet CaglanErsen BalcisoyEmre KirkayaGurbannazar CharyyevAdem ÇiçekEnver CavusPublished in: SIU (2017)
Keyphrases
- error correction
- fpga implementation
- low density parity check
- ldpc codes
- channel coding
- hardware implementation
- error detection
- data hiding
- error correcting
- joint source channel coding
- error control
- reed solomon
- turbo codes
- decoding algorithm
- signal processing
- error resilient
- distributed video coding
- computer simulation