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A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems.
Youchang Kim
Gyeonghoon Kim
Injoon Hong
Donghyun Kim
Hoi-Jun Yoo
Published in:
A-SSCC (2014)
Keyphrases
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neural network
network on chip
multi core systems
routing algorithm
power consumption
network simulator
multi core processors
power dissipation
shared memory
real time
scheduling algorithm
sensor networks
packet loss