A Power and Area Efficient 65 nm CMOS delay-Line ADC for on-Chip voltage Sensing.
Sida Amy ShenShuang XieWai Tung NgPublished in: J. Circuits Syst. Comput. (2013)
Keyphrases
- power consumption
- silicon on insulator
- cmos technology
- high speed
- analog vlsi
- low cost
- low voltage
- nm technology
- chip design
- image sensor
- high density
- single chip
- power dissipation
- power management
- low power
- ibm power processor
- sensor networks
- circuit design
- metal oxide semiconductor
- transmission line
- power supply
- analog to digital converter